книга M6800 Microprocessor Applications Manual

А Б В Г Д Е Ж З И К Л М Н О П Р С Т У Ф Х Ц Ч Ш Щ Э Ю Я
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M6800 Microprocessor Applications Manual

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Название: M6800 Microprocessor Applications Manual
Автор: Motorola Inc.
Страниц: 713
Формат: PDF
Размер: 38 Мб
Качество: Отличное
Язык: Английский
Год издания: 1975


Motorola has elected to provide a microprocessor family of parts headed by the MC6800 Microprocessing Unit (MPU).The MC6800 MPU is an eight-bit parallel microprocessor with addressing capability of up to 65,536 words. It is TTL compatible requiring only a single five-volt supply and no external TTL devices for bus interface in small systems.



Table of contents


Chapter 1
1 Introduction to the MC6800 Microprocessor
1-1 System Organization
1-1-1 MC6800 Family Elements
1-1-1-1 Memory on the Bus
1-1-1-2 I/O on the Bus
1-1-2 Typical System Configuration
1-1-2-1 Memory Allocation
1-1-2-2 Hardware Requirements

1-2 Source Statements and Addressing Modes
1-2-1 Source Statements
1-2-2 Labels
1-2-3 Addressing Modes
1-2-3-1 Inherent (Includes "Accumulator Addressing" Mode)
1-2-3-2 Immediate Addressing Mode
1-2-3-3 Direct and Extended Addressing Modes
1-2-3-4 Relative Addressing Mode
1-2-3-5 Indexed Addressing Mode
1-2-3-6 Mode Selection


1-3 Instruction Set
1-3-1 Condition Code Register Operations
1-3-2 Number Systems
1-3-3 Accumulator and Memory Operations
1-3-3-1 Arithmetic Operations
1-3-3-2 Logic Operations
1-3-3-3 Data Test Operations
1-3-3-4 Data Handling Operations
1-3-4 Program Control Operations
1-3-4-1 Index Register/ Stack Pointer Operations
1-3-4-2 Jump and Branch Operations

Chapter 2
2 Programming Techniques
2-1 Arithmetic Operation
2-1-1 Number Systems
2-1-2 The Condition Code Register
2-1-3 Overflow
2-1-4 The Arithmetic Instructions
2-1-4-1 Use of Arithmetic Instructions
2-1-5 Addition and Subtraction Routines
2-1-6 Multiplication
2-1-7 Division
2-2 Counting and Delay Measurement/Generation
2-3 Evaluating Peripheral Control Routines
2-3-1 Service Requests and Programs as Waveforms on a Timing Diagram - Notation Used
2-3-2 Development of Equations and Inequalities Used to Test Successful System Operations
2-3-3 Floppy Disk Data Transfer Routine
2-3-5 Cassette Data Transfer Routine
2-3-6 Program Model for two Prioritized Service Requests
2-3-7 Requirements That Must Be Satisfied When an MPU Services Multiple SR's
2-3-8 Serial Data Transfer and Dynamic Refresh Processing
2-3-9 Increasing MPU Processing Efficiency with the Flip-Flop Model for Two "Equal Period SR's"
2-4 Use of the Index Register

Chapter 3
3 Input/output Techniques
3-1 Introduction
3-2 MC6800 Interrupt Sequences
3-2-1 Interrupt Request (!IRQ)
3-2-2 Non Maskable Interrupt (!NMI)
3-2-3 Reset (RES)
3-2-4 Software Interrupt (!SWI)
3-3 Interrupt Prioritizing
3-4 Program Controlled Data Transfer
3-4-1 MC6820 Peripheral Interface Adapter
3-4-1-1 Input/Output Configuration
3-4-1-2 Internal Organization
3-4-1-3 Addressing and Initialization
3-4-1-4 System Considerations
3-4-2 MC6850 Asynchronous Communications Interface Adapter
3-4-2-1 Input/Output Configuration
3-4-2-2 Internal Organization
3-4-2-3 Addressing and Initialization
3-4-2-4 System Considerations
3-4-3 MC6860 Low Speed Modem
3-4-3-1 Input/Output Configuration
3-4-3-2 Internal Organization
3-4-3-3 Handshake and Control
3-5 Direct Memory Access

Chapter 4
4 M6800 Family Hardware Characteristics
4-1-1 Clock Circuitry for the MC6800
4-1-1-1 Clock Requirements and Circuitry
4-1-1-2 Clock Module
4-1-2 Halting the MC6800 and Single Instruction Execution
4-1-3 MC6800 Reset and Interrupt Controls
4-1-4 Three State Control Line Operations
4-1-5 M6800 System Hardware Techniques
4-2 M6800 System Hardware Techniques
4-2-1 Interrupt Priority Circuitry
4-2-1-1 8-Level Prioritizing
4-2-1-2 13-Level Prioritizing
4-2-2 Direct Memory Access (DMA)
4-2-2-1 DMA Transfers by Halting Processor
4-2-2-2 DMA Transfers by Cycle Stealing
4-2-2-3 Multiplexed DMA/MPU Operation
4-2-2-4 Summary of DMA Techniques
4-2-3 Automatic Reset and Single Cycle Execution Circuitry
4-2-4 Interval Timer
4-2-5 Memory System Design
4-2-5-1 Interfacing the MC6800 with Slow and Dynamic Memories
4-2-5-2 2Kx8 RAM Memory Design Example
4-2-5-3 8Kx8 Non-Volatile RAM Design Example
4-2-5-4 Design Considerations When Using Non-Family Memories with the MC6800

Chapter 5
5 Peripheral Control Techniques
5-1 Data Input Devices
5-1-1 Keyboards for Manual Entry of Data
5-1-1-1 Decoded Keyboard for a POS Terminal
5-1-1-2 Non Encoded Keyboard
5-1-2 Scanning Wand for Capturing Data from Printed Symbols
5-1-2-1 Universal Product Code (UPC) Symbol
5-1-2-2 Hardware Requirements
5-1-2-3 Data Recovery Technique
5-1-2-4 Wand/MPU Interface
5-1-2-5 Data Recovery Control Program
5-2 Data Output Devices
5-2-1 Printer Control
5-2-1-1 SEIKO AN-101F Operating Characteristics
5-2-1-2 Printer Hardware/ Sofware Tradeoffs
5-2-1-3 Printer I/O Configuration
5-2-1-4 Printer Control Program
5-2-2 Burroughs Self-Scan Display Control
5-3 Data Interchange Devices
5-3-1 Introduction to Data Communications
5-3-1-1 TTY to ACIA Hardware
5-3-1-2 TTY to ACIA Software
5-3-1-3 ACIA to Modem Harware
5-3-1-4 ACIA to Modem Software
5-3-2 Tape Cassette System
5-3-2-1 Hardware Description
5-3-2-2 Software Description
5-4 Floppy Disk
5-4-1 Introduction
5-4-2 Overall Considerations
5-4-3 System Hardware/Software Interface
5-4-4 Disk Program Routine Linking Control
5-4-5 Seek and Restore Operations
5-4-6 Read Operation
5-4-6-1 The Read Operation Interface
5-4-6-2 Data Recovery
5-4-6-3 Read Data Logic
5-4-6-4 Read Operation Program Routine
5-4-7 Write Operation
5-4-7-1 The Write Operation Interface
5-4-7-2 Formatter Write Logic
5-4-7-3 Formatter Error Detect Logic
5-4-7-4 Write Operation Program Routine
5-4-8 Special Operations - UPC lookup
5-4-9 Integrated Read/Write Logic
5-4-A SA900/901 Diskette Storage Drive
5-4-B Orbis Model 74 Diskette Drive
5-4-C Cal Comp 140 Diskette Drive
5-4-D Recording Formats
5-4-E Floppy Disk Program Listings

Chapter 6
6 System Design Techniques
6-1 Introduction
6-2 Transaction Terminal Definition
6-3 Hardware/Software Tradeoffs
6-3-1 Memory Reference I/O vs DMA I/O
6-3-2 Sofware vs Harware Peripheral Service Prioritizing
6-3-3 Software vs Hardware Timer
6-3-4 Display With or Whitout Memory
6-4 Transaction Terminal Hardware and Software
6-4-1 Hardware Configuration
6-4-2 Transaction Terminal Software Development
6-4-2-1 Software Background Preparation
6-4-2-2 Development of Macro Flow Diagram
6-4-2-3 Technique of Executive Program Organization
6-4-2-4 Description of Macro Flow Diagram
6-4-3 Interrupt Control

Chapter 7
7 System Development Tasks
7-1 Assembly of the Control Program
7-1-1 M6800 Cross-Assembler Syntax
7-1-1-1 Line Numbers
7-1-1-2 Fields of the Source Statement
7-1-1-3 Labels
7-1-1-4 Operands
7-1-1-5 Comments
7-1-2 Accessing a Timeshare Service
7-1-3 Entering a Source Program
7-1-4 Assembling a Source Program
7-1-5 Simulation
7-1-5-1 Simulator Comands
7-1-5-2 Operating the Simulator
7-1-5-3 Macro Commands
7-1-5-4 Sample Simulated Program
7-1-5-5 Simulation Results
7-1-6 HELP
7-1-7 Build Virtual Machine
7-2 The EXORciser
7-2-1 Hardware Components
7-2-1-1 Hardware Specification
7-2-2 Software Components
7-2-2-1 EXORciser Control
7-2-2-2 MAID
7-2-3 Memory utilization
7-2-4 Hardware Operations and Controls
7-2-4-1 Hardware Operations and Controls
7-2-4-2 ABORT Button Circuit
7-2-4-3 RESTART Button Circuit
7-2-4-4 VMA Inhibit Decoder
7-2-4-5 Asynchronous Communications Interface
7-2-4-6 Scope SYNC
7-2-5 Interrupts
7-2-5-1 !NMI
7-2-5-2 !RESET
7-2-5-3 SWI
7-2-5-4 Hardware Interrupt
7-2-6 Test Signals
7-3 Evaluation Module

APPENDIX A: Questions and Answers

1 System Operation
2 Control
3 Interrupt Operation
4 Programming


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